This application is based upon and claims priority from prior European Patent Application No. 98-830067.9, filed Feb. 13, 1998, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to memory devices, and more specifically to a sense amplifier for memories that operate in an extended supply voltage range.
2. Description of Related Art
In the following description, reference is made to conventional terms used in MOS (Metal Oxide Semiconductor) transistor technology. For example, the term xe2x80x9cgatexe2x80x9d indicates the control electrode or input electrode of a MOS transistor, the term xe2x80x9cdrainxe2x80x9d indicates the load electrode or output electrode, and the term xe2x80x9csourcexe2x80x9d indicates the source electrode or output electrode. Further, the term xe2x80x9cnon-volatilexe2x80x9d memory indicates a memory that does not lose stored data when the power supply is shut off, such as a ROM (Read Only Memory), EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), and EAROM (Electrically-Alterable Read Only Memory).
In EEPROM memories, data is stored by a transistor with a floating gate. A positive or negative electric charge is captured on the floating gate to modify the transistor threshold and store either a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d logic state. If no charges are trapped on the floating gate, the memory cell is known as xe2x80x9cvirginxe2x80x9d; otherwise, it is known as xe2x80x9cwrittenxe2x80x9d or xe2x80x9cerasedxe2x80x9d. The logic state, charge sign, and cell state (erased or written) depend on standards that can change from one product to another. The logic state of an EEPROM cell is detected based on the current that flows through the cell under known conditions.
If a negative charge is trapped on the floating gate, the cell threshold is higher than that of a virgin cell. On the other hand, if a positive charge is trapped, the threshold is lower. Generally, stored information is recovered by comparing a cell""s current with the current of a virgin cell subject to the same conditions using an amplifier known as a xe2x80x9csense amplifierxe2x80x9d. In conventional sense amplifiers, this operation is carried out by a current/voltage conversion in two different branches in which such currents are flown. As shown in FIG. 1, convention sense amplifiers are typically based on a current mirror between the two branches.
In the conventional device, drains of memory cells CELL (which are organized in a matrix) are connected to a xe2x80x9cbit linexe2x80x9d BL, and a decoder (not shown) selects one of the cells. A circuit is connected to the bit line BL of the selected cell, and an identical circuit is connected to a virgin cell that is located outside of the matrix. The drain of the reference cell REF is connected in a fully symmetrical mode with the bit line BLREF. The currents from these two cells are converted into voltages VDREF and VDCELL through a current/voltage converter, which is formed by two transistors P1 and P2 (usually P-channel MOS transistors in a current mirror configuration as shown in FIG. 1).
The two voltages VDREF and VDCELL are supplied to the inputs of a differential comparator AMP that compares the voltages and delivers a logic value representative of the state of the cell being read. Generally, the differential comparator AMP is a classic source coupling differential stage NMOS with an active load represented by a PMOS transistor, as shown in FIG. 2. However, such a conventional configuration has limitations in low power applications as will be explained below. As shown in FIG. 1, on the reference side, a circuit is connected to the drain of the reference cell REF. This circuit includes an N-channel MOS transistor N1 whose control electrode is driven by an inverter INV1 that is controlled by the voltage on the reference bit line BLREF.
A polarization voltage for the bit line VBL is applied by this circuit (i.e., on the drain of the reference cell REF) with the bit line polarization voltage VBL being high enough to supply a voltage between the drain and source VDS to allow the cell to be read. The polarization voltage of the bit line VBL is a function of the threshold voltage or inversion of the inverter INV1 and the threshold voltage VTN1 of the transistor N1. A load such as the P-channel transistor shown in FIG. 1 connects the transistor drain N1 with the supply voltage VDD. The current IREF flowing through the reference cell REF and the transistor N1 is reflected in the sense amplifier for the cell being read. For this purpose, the transistor P1 is diode connected and reflects the current IREF1 in the other (identical) transistor P2.
The differential comparator AMP shown in FIG. 2 can operate linearly to ensure a correct comparison between the voltages VDREF and VDCELL, except this results in a lower limit for the voltage VDREF, which equals the voltage drop determined in the differential amplifier by the threshold voltage of the active load transistor, plus the overvoltage on the active load, plus the drain source voltage drop on the polarization transistor. At the same time, the voltage VDREF is a function of the supply voltage VDD less the voltage drop due to the threshold voltage of the transistor P1 and overdrive voltage due to the current mirror reflection IREF. Therefore, if the supply voltage VDD falls below 2 V, the differential comparator AMP of the conventional sense amplifier will not be able to operate correctly in its amplifying range. Because of this drawback, a different circuit is required to ensure an efficient functionality of the read operation at low supply voltages.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a sense amplifier having a simple comparator scheme with good switching performance over an extended voltage range.
One embodiment of the present invention provides a sense amplifier that includes a comparator and a bit line polarization circuit. The comparator receives a first signal representative of a current flowing through a memory cell and a second signal representative of a reference current. Additionally, the comparator includes a stage in a common source configuration and an active load for the stage, and the bit line polarization circuit provides a polarization voltage level that is independent of the supply voltage level. In a preferred embodiment, the sense amplifier also includes an output stage that improves switching time at high supply voltages.
Another embodiment of the present invention provides a method for sensing logic levels in a memory device. According to the method, a bit line is polarized at a polarization voltage level, and a first signal representative of a current flowing through a memory cell is compared with a second signal representative of a reference current. The polarization voltage level is independent of the supply voltage level. In one preferred method, the polarization voltage level is generated using a steady current that is externally generated.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.